A junction field effect transistor (JFET) used for switching of an inverter and the like is required to endure high current and high voltage. FIG. 25 is a diagram representing a normal horizontal JFET. In the horizontal JFET, carriers move substantially parallel to the semiconductor substrate surface. A ground potential is applied to a source region 101 through a source electrode 111, and a positive potential is applied to a drain region 103 through a drain electrode 113. A pn junction is formed below a gate region 102 beneath gate electrode 112, and when the device is caused to attain an off-state, a negative voltage is applied to gate electrode 112 such that this junction portion attains the reverse bias state. When the device is in an on-state, electrons in source region 101 are attracted by the positive potential of drain region 103, pass through a channel region 110 under gate region 102, and reach drain region 103.
In the above-described horizontal JFET, the source electrode, the gate electrode, and the drain electrode are located in the same plane as shown in FIG. 25 so that the drain electrode and other electrodes would be close with air existing therebetween. Since breakdown electric field of air is 3 kV/mm at most, there was a need to place the drain electrode away from other electrodes by at least 1 mm when a voltage of 3 kV or greater was applied between the drain electrode and other electrodes in the off-state in which no current flowed. Consequently, the length of a channel region 109 leading from source region 101 to drain region 103 became long, and only a small current could be allowed to flow, so that a high current required for a so-called power transistor could not be allowed to flow.
FIG. 26 is a diagram representing a vertical JFET, also called a static induction transistor (hereinafter, referred to as an SIT), that is proposed and practically utilized so as to provide improvement upon the weakness of the above-described horizontal JFET. Unlike the horizontal JFET, the carriers move substantially in the direction of thickness of the semiconductor substrate in the vertical JFET. In an SIT, a plurality of gate regions 102 are formed as p+ regions in which p type impurity of high concentration is implanted, and n− region having n type impurity of low concentration added is formed therearound. Since the n type impurity concentration in the n− region is low, a depletion layer expands at all times and the channel region is vanished. As a result, the saturation phenomenon of a drain current due to a pinch-off that occurs in the above-described horizontal JFET does not take place. The method of potential application to each of the source region, the gate region, and the drain region is the same as that of the horizontal JFET shown in FIG. 25. The electrons in source region 101 overcome the potential barrier of the gate region, are attracted to the drain potential, and drift in the depletion layer. When the drain potential is set to a high positive potential, the potential barrier against the electrons of the gate region becomes small, which allows an increase in a drift current. Thus, the saturation phenomenon of the drain current would not take place even when the drain potential is raised. The drain current is normally controlled by a gate potential and a drain potential. When the above-described SIT is utilized for switching, in order to obtain a large current, the voltage had to be set high so as to allow the electrons to overcome the potential barrier, which inevitably resulted in a certain loss, though small.
Moreover, when a JFET was caused to attain the off-state in the switching operation, there was a need to apply a negative voltage whose absolute value exceeded 10V to a gate electrode in order to pinch off the channel region with the depletion layer. Since the application of such negative voltage having a large absolute value causes power loss also in the off-state, it is desirable to realize the off-state without any power loss.
Furthermore, in general, the impurity concentration of a channel region in a JFET is subjected to restrictions in order to ensure a prescribed transistor characteristic, so that it cannot be set too high. Consequently, the electric resistance of the channel region tends to increase, and what is more, the electric resistance varies according to the impurity concentration, the thickness of the channel region, and so on. The transistor characteristic is strongly influenced by the electric resistance of the above-described channel region so that it varies significantly according to the variations in the impurity concentration, the thickness and the like. If, in order to avoid such variations at each devices, an impurity element of a high concentration is implanted for the purpose of reducing the electric resistance in the channel region, the withstand voltage performance would be degraded. Thus, there was a demand for a JFET that has the reduced on-resistance without the use of an impurity of a high concentration and that is less likely to be affected by variations in the impurity concentration of the channel region, the thickness of the channel region, and so on.